ASIC Design Engineer, BOOT, Functional Safety and Power Management

NVIDIA · India, Bengaluru · Posted 1 month ago

About this role

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for RTL Design engineers for our BOOT, Functional Safety and Power management Subsystem Design deployed in Automotive and Client chips. As one of the primary designers, you will be responsible for implementing independent BOOT, functional safety and overall power management architecture of next generation chips. One should possess strong digital design and verification fundamentals. What you'll be doing: As a designer, be responsible for making architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. During the course of a project you would end up driving the following aspects of design for your unit: Own micr