Design Verification - SoC, ASIC System Verilog, UVM

HCLTech · India · Remote · Posted Yesterday

About this role

As an experienced Design Verification Engineer at HCL Tech., Bangalore, your role will involve the following responsibilities: - Lead and define endtoend verification strategy for complex ASIC/SoC programs - Architect and develop robust UVM-based verification environments and testbenches - Leverage advanced verification methodologies including UVM, Formal Verification, and Assertions - Work handson with industry-leading tools such as simulators, formal tools, and debuggers - Debug complex failures, perform root-cause analysis, and partner with design teams - Drive code quality, enforce best practices, and participate in design/code reviews - Mentor and guide junior DV engineers to foster a highperformance technical culture - Stay updated with emerging verification technologies, tools, and methodologies - Influence the verification roadmap and contribute to technical decision-making Qualifications required for this position include: - Masters (preferred) or Bachelors degree in Electrical/Computer Engineering - 10+ years of experience in Design Verification for complex ASIC/SoC designs - Handson expertise with UVM, SystemVerilog, Verilog/VHDL, and Assertions - Deep understanding of digital design fundamentals - Strong experience with simulators, formal verification tools, and scripting (Perl/Python/Tcl) - Proven track record of leading verification teams and driving project success - Excellent communication, leadership, analytical, and troubleshooting skills - Ability to handle